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- 1 - k4m51323pi rev. 1.0, dec. 2009 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2009 samsung electronics co., ltd. all rights reserved. 512mb i-die mobile sdr sdram 16mb x32, 90fbga with lead-free & halogen-free (vdd / vddq = 1.8v / 1.8v) datasheet
- 2 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 revision history revision no. history draft date remark editor 0.0 -first version for target specif ication. nov. 23, 2009 target j.y.bae 1.0 - final datasheet. dec. 18, 2009 final j.y.bae - revised dc characteristics. 1. icc1 : 70/60 -> 65/60 @ 166mhz, 133mhz [ma] 2. icc2ns : 1/1 -> 5/4 @ 166mhz, 133mhz [ma] 3. icc3p : 5/5 -> 3/3 @ 166mhz, 133mhz [ma] 4. icc3n : 20/15 -> 12/12 @ 166mhz, 133mhz [ma] 5. icc3ns : 10/8 -> 8/8 @ 166mhz, 133mhz [ma] 6. icc4 : 80/70 -> 65/60 @ 166mhz, 133mhz [ma] 7. icc5 : 80/80 -> 70/70 @ 166mhz, 133mhz [ma]
table of contents - 3 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 512mb i-die mobile sdr sdram 1.0 features................................................................................................................... .............................................. 4 2.0 general description ........................................................................................................ ................................. 4 3.0 ordering information ....................................................................................................... ............................... 4 4.0 address configuration .. .............. .............. .............. .............. ........... ........... ........... ........... ............................. 4 5.0 functional block diagram ................................................................................................... ........................... 5 6.0 package dimension and pin configuration .................................................................................... .......... 6 7.0 absolute maximum rating s ............... .............. .............. .............. .............. .............. .............. .......................... 7 8.0 dc operating conditions .................................................................................................... ............................. 7 9.0 capacitance ........ .............. .............. .............. .............. .............. .............. ........... ......... .......................................... 7 10.0 dc characteristics........................................................................................................ .................................. 8 11.0 ac operating test conditions .............................................................................................. ....................... 9 12.0 operating ac parameter .................................................................................................... ........................... 10 13.0 ac characteristics ........................................................................................................ .................................. 11 14.0 simplified truth table .................................................................................................... ................................ 12 15.0 mode register field table to program modes ................................................................................ .... 13 15.1 register programmed with normal mrs ................. ...................................................................... ....................... 13 15.2 normal mrs mode ........................................................................................................... ..................................... 13 15.3 register programmed with exten ded mrs ........... .............. .............. .............. ........... ............ ......... ...................... 13 15.4 emrs for pasr(partial array se lf ref.) & ds(d river strength) ............................................................... .........13 15.4.1 partial array self refres h.............................................................................................. .................................. 14 15.4.2 internal temperature compensated self refresh (tcsr) .................................................................... ......... 14 16.0 power up sequence ......................................................................................................... ................................ 14 17.0 burst sequence............................................................................................................ ..................................... 15 17.1 burst length = 4.......................................................................................................... ................................... 15 17.2 burst length = 8 ............................................................... ............................................................... ........15
- 4 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 4m x 32bit x 4 banks mob ile sdr sdram in 90fbga 1.0 features ? vdd/vddq = 1.8v/1.8v ? lvcmos compatible with multiplexed address. ? four banks operation. ? mrs cycle with address key programs. -. cas latency (2 & 3). -. burst length (1, 2, 4, 8 & full page). -. burst type (sequential & interleave). ? emrs cycle with address key programs. ? all inputs are sampled at the pos itive going edge of the system clock. ? burst read single-bit write operation. ? special function support. -. pasr (partial array self refresh). -. internal tcsr (temperature compensated self refresh) -. ds (driver strength) ? dqm for masking. ? auto refresh. ? 64ms refresh period (8k cycle). ? extended temperature operation (-25 c ~ 85 c). ? commercial temperature operation (-25 c ~ 70 c). ? 90balls fbga( -sxxx -pb, -dxxx -pb free). 2.0 general description the k4m51323pi is 536,870,912 bits synchronous high data rate dynam ic ram organized as 4 x 4,194,304 words by 32 bits, fabricat ed with sam- sung?s high performance cmos technology. sync hronous design allows precise cycle control with the use of system clock and i/o t ransactions are pos- sible on every clock cycle. range of operat ing frequencies, programmable burst lengths and programmable latencies allow the sam e device to be useful for a variety of high bandwidth and high performance memory system applications. 3.0 ordering information - k4m51323pi- h g60/75 : 90fbga (pb free, halogen free) - k4m51323pi-h g 60/75 : low power, extended temperature(-25 c ~ 85 c) 4.0 address configuration part no. max freq. interface package k4m51323pi-hg60 166mhz(cl=3) lvcmos 90 fbga (pb free) k4m51323pi-hg75 133mhz(cl=3),83mhz(cl=2) organization bank address row address column address 16mx32 ba0,ba1 a0 - a12 a0 - a8
- 5 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 5.0 functional block diagram bank select data input register 4m x 32 4m x 32 sense amp output buffer i/o control column decoder latency & burst length programming register address register row buffer refresh counter row decoder col. buffer lras lcbr lcke lras lcbr lwe ldqm clk cke cs ras cas we dqm lwe ldqm dqi clk add lcas lwcbr 4m x 32 4m x 32 timing register
- 6 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 6.0 package dimension and pin configuration 90ball(6x15) fbga 123789 a dq26 dq24 v ss v dd dq23 dq21 bdq28v ddq v ssq v ddq v ssq dq19 cv ssq dq27 dq25 dq22 dq20 v ddq dv ssq dq29 dq30 dq17 dq18 v ddq ev ddq dq31 nc nc dq16 v ssq fv ss dqm3 a3 a2 dqm2 v dd g a4 a5 a6 a10 a0 a1 h a7 a8 a12 nc ba1 a11 jclkcke a9 ba0 cs ras kdqm1 nc nc cas we dqm0 lv ddq dq8 v ss v dd dq7 v ssq mv ssq dq10 dq9 dq6 dq5 v ddq nv ssq dq12 dq14 dq1 dq3 v ddq pdq11v ddq v ssq v ddq v ssq dq4 r dq13 dq15 v ss v dd dq0 dq2 pin name pin function clk system clock cs chip select cke clock enable a 0 ~ a 12 address ba 0 ~ ba 1 bank select address ras row address strobe cas column address strobe we write enable dqm 0 ~ dqm 3 data inputs/outputs mask dq 0 ~ 31 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground < bottom view *1 > < top view *2 > symbol min typ max a- -1.00 a 1 0.25 - - e 7.9 8.0 8.1 e 1 -6.40- d 12.9 13.0 13.1 d 1 -11.2- e - 0.80 - b 0.45 0.50 0.55 z--0.10 [unit::mm] 521 63 4 8 97 f e d c b j h g a e d d 1 e 1 e m l k r p n z a a1 b *2: top view *1: bottom view < top view *2 > #a1 ball origin indicator k4m51323pi-xxxx samsung week
- 7 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 7.0 absolute maximum ratings note : 1) permanent device damage may occur if absolute maximum ratings are exceeded. 2) functional operation should be restricted to recommended operating condition. 3) exposure to higher than recommended voltage for exte nded periods of time could affect device reliability. 8.0 dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, tc = -25 to 85 c for extended) note : 1) under all conditions, vddq must be less than or equal to vdd. 2) vih (max) = 2.2v ac.the overshoot voltage duration is 3ns. 3) vil (min) = -1.0v ac. the undershoot voltage duration is 3ns. 4) any input 0v vin vddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 5) dout is disabled, 0v vout vddq. 9.0 capacitance (v dd = 1.8v, tc = 23 c, f = 100mhz, v ref =0.9v 50 mv) parameter symbol value unit voltage on any pin relative to v ss v in , v out -1.0 ~ 2.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 2.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma parameter symbol min max unit note supply voltage v dd 1.7 1.95 v 1 v ddq 1.7 1.95 v 1 input logic high voltage for add. v ih 0.8 x v ddq v ddq + 0.3 v 2 for dq 0.7 x v ddq v ddq + 0.3 v input logic low voltage for add. v il -0.3 0.2 v 3 for dq -0.3 0.3 v output logic high voltage v oh v ddq -0.2 - v i oh = -0.1ma output logic low voltage v ol - 0.2 v i ol = 0.1ma input leakage current i li -2 2 ua 4 pin symbol min max unit note adds(a0 ~ a12, ba0 ~ ba1), ras ,cas , we cin1 1.5 3.0 pf cs cin2 1.5 3.0 pf cke cin3 1.5 3.0 pf clk cin4 1.5 3.5 pf dqms cin5 1.5 3.0 pf dqs(dq0 ~ dq31) cout 2.0 4.5 pf
- 8 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 10.0 dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, tc = -25 to 85 c for extended) note : 1) measured with outputs open. 2) refresh period is 64ms. 3) icc5 is measured under the below test condition. 4) internal tcsr can be supported. 5) dpd(deep power down) function is an optional feature, and it will be enabled upon request. please contact samsung for more information. 6) unless otherwise noted, i nput swing ievei is cmos(v ih /v il =v ddq /v ssq ). parameter symbol test condition version unit note -60 -75 operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) io = 0 ma 65 60 ma 1 precharge standby current in power-down mode i cc2p cke v il (max), t cc = 10ns 0.3 0.3 ma i cc2ps cke & clk v il (max), t cc = 0.3 0.3 precharge standby current in non power-down mode i cc2n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 10 8 ma i cc2ns cke v ih (min), clk v il (max), t cc = input signals are stable 5 4 active standby current in power-down mode i cc3p cke v il (max), t cc = 10ns 3 3 ma i cc3ps cke & clk v il (max), t cc = 2 2 active standby current in non power-down mode (one bank active) i cc3n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 12 12 ma i cc3ns cke v ih (min), clk v il (max), t cc = input signals are stable 8 8 ma operating current (burst mode) i cc4 io = 0 ma page burst 4banks activated t ccd = 2clks 65 60 ma 1 refresh current i cc5 t arfc t arfc 70 70 ma 2,3 self refresh current i cc6 cke 0.2v tcsr range values typ max full array 85 c 400 500 ua 4 70 c 250 45 c 150 250 15 c 140 1/2 array 85 c 300 400 ua 70 c 200 45 c 120 220 15 c 110 1/4 array 85 c 250 350 ua 70 c 165 45 c 100 200 15 c 95 density 128mb 256mb 512mb 1gb 2gb unit tarfc 80 80 110 140 140 ns
- 9 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 11.0 ac operating test conditions (vdd = 1.7 ~ 1.95 v, tc = -25 ~ 85 c for extended) figure 1. dc output load circuit figure 2. ac output load circuit 1), 2) note : 1) the circuit shown above repr esents the timing reference load used in defin ing the relevant timing parameters of the part. it is not intended to be either a precise representa- tion of the typical system environment nor a depiction of the ac tual load presented by a production tester. system designers wi ll used ibis or other simulations tools to correlate the timing reference load to system environment. manufacturers wil l correlate to their poduction test conditions (generally a c oaxial transmission line terminated at the tester electronics). for the half strength driver with a nominal 10pf lo ad parameters tac and tqh are expected to be in ther same rang e. however, these parameters are not subject to production test but are estimated by design / characterization. use of ibis or other simulation tolls for system design vali dation is suggested. 2) based on nominal impedance at 0.5 x vddq. the impedence for half(1/2) driver strength is designed 55ohm. and for other driver strength, it is designed proportionally. parameter value unit ac input levels (vih/vil) 0.9 x v ddq / 0.2 v input timing measurement reference level 0.5 x v ddq v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 0.5 x v ddq v output load condition see figure 2 vddq 13.9k ? 10.6k ? output 20pf voh (dc) = vddq - 0.2v, ioh = -0.1ma vol (dc) = 0.2v, iol = 0.1ma vtt=0.5 x vddq 50 ? output 20pf z0=50 ? test load values need to be proportional to the driver strength which is set by the controller. - test load for full driver strength buffer (20pf) - test load for half driver strength buffer (10pf)
- 10 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 12.0 operating ac parameter (ac operating conditions unless otherwise noted) note : 1) the minimum number of clock cycles is determined by divi ding the minimum time required with clock cycle time and then roundi ng off to the next higher integer. 2) minimum delay is required to complete write. 3) t dal =(t rdl /t cc )+(t rp /t cc ) in case of below 33mhz (tcc = 30ns ) condition, sec could support tdal (=2*t ck ) 4) all parts allow every cycle column address change. 5) in case of row precharge interrupt, auto precharge and read burst stop. 6) maximum burst refresh cycle : 8 parameter symbol version unit note -60 -75 row active to row active delay t rrd (min) 12 15 ns 1 ras to cas delay t rcd (min) 18 22.5 ns 1 row precharge time t rp (min) 18 22.5 ns 1 row active time t ras (min) 42 50 ns 1 t ras (max) 100 us row cycle time t rc (min) 60 72.5 ns 1 last data in to row precharge t rdl (min) 15 ns 2 last data in to active delay t dal (min) t rdl + t rp - 3 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 auto refresh cycle time t arfc (min) 80 ns 6 exit self refresh to active command t srfx (min) 120 ns col. address to col. address delay t ccd (min) 1 clk 4 number of valid output data cas latency=3 2 ea 5 cas latency=2 1
- 11 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 13.0 ac characteristics (ac operating conditions unless otherwise noted) note : 1) parameters depend on programmed cas latency. 2) t cc (max) value is measured at 100ns. 3) the only time that the clock frequency is allowed to be changed is during clock stop, power-down, self-refresh modes. 4) if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 5) assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, trans ient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. parameter symbol -60 -75 unit note min max min max clk cycle time cas latency=3 t cc 6.0 1000 7.5 1000 ns 1,2,3 cas latency=2 - 12 clk to valid output delay cas latency=3 t sac 5.4 6 ns 1,4 cas latency=2 9 output data hold time cas latency=3 t oh 2.5 2.5 ns 4 cas latency=2 - 2.5 clk high pulse width t ch 2.5 2.5 ns 5 clk low pulse width t cl 2.5 2.5 ns 5 input setup time t ss 2.0 2.0 ns 5 input hold time t sh 1 1 ns 5 clk to output in low-z t slz 1 1 ns 4 clk to output in hi-z cas latency=3 t shz 5.4 6 ns cas latency=2 - 9
- 12 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 14.0 simplified truth table note : 1) op code : operand code a0 ~ a12 & ba0 ~ ba1 : program keys. (@mrs) 2) mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3) auto refresh functions are the same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. partial self refresh can be issued only after setting partial self refresh mode of emrs. 4) ba0 ~ ba1 : bank select addresses. 5) during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 6) burst stop command is valid at every burst length. 7) dqm sampled at the positive going edge of clk masks the data-in at that same clk in write oper ation (write dqm latency is 0) , but in read operation, it makes the data-out hi-z state after 2 clk cycles. (read dqm latency is 2). command cken-1 cken cs ras cas we dqm ba0,1 a10/ap a12,11, a9 ~ a0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a0~a8) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a0~a8) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l h h h exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l h h h dqm h x v x 7 no operation command h x h x x x x x l h h h
- 13 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 15.0 mode register field table to program modes 15.1 register programmed with normal mrs 15.2 normal mrs mode 15.3 register programmed with extended mrs 15.4 emrs for pasr(partial array self ref.) & ds(driver strength) note : 1) rfu(reserved for future use) should stay "0" during mrs cycle. 2) if a9 is high during mrs cycle, "burst read single bit write" function will be enabled. 3) full page length x32 : 64mb(256) , 128mb (256), 256mb (512), 512mb (512) address ba0 ~ ba1 a12 ~ a10/ap a9 2) a8 a7 a6 a5 a4 a3 a2 a1 a0 function "0" setting for normal mrs rfu 1) w.b.l test mode cas latency bt burst length test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 reserved 0 0 1 reserved 1 interleave 0 0 1 2 2 1 0 reserved 0 1 0 2 mode select 0 1 0 4 4 1 1 reserved 0 1 1 3 ba1 ba0 mode 0 1 1 8 8 write burst length 1 0 0 reserved 0 0 setting for normal mrs 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 full page 3) reserved address ba1 ba0 a12 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function mode select rfu 1) ds rfu 1) pasr mode select driver strength pasr ba1 ba0 mode a7 a6 a5 driver strength a2 a1 a0 # of banks 0 0 normal mrs 0 0 0 full 0 0 0 full array 0 1 reserved 0 0 1 1/2 0 0 1 1/2 array 1 0 emrs 0 1 0 1/4 0 1 0 1/4 array 1 1 reserved 0 1 1 1/8 0 1 1 reserved 100 3/4 1 0 0 reserved reserved address 101 3/8 1 0 1 reserved a12~a10/ap a9 a8 a4 a3 110 5/8 1 1 0 reserved 0 0000111 7/8 1 1 1 reserved
- 14 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 15.4.1. partial array self refresh 1. in order to save power consumption, mobile sdr sdram has pasr option. 2. mobile sdr sdram supports 3 kinds of pasr in se lf refresh mode : full array, 1/2 array, 1/4 array 15.4.2. internal temperature compensated self refresh (tcsr) 1. in order to save power consumption, this mobile dram inclu des the internal temperature sens or and control units to control t he self refreshcycle auto- matically according to the real device temperature. 2. tcsr ranges for idd6 shown in the table are as an example only. max idd6 valus for 45 c, 85 c are guaranteed. typical values for 85 c, 70 c, 45 c and 15 c are obtained from dev ice characterization. 3. if the emrs for external tcsr is issued by th e controller, this emrs code for tcsr is ignored. 16.0 power up sequence 1. apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply vdd before or at the same time as vddq. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. 6. issue a extended mode register set command fo r the desired operating modes after normal mrs. the mode register and extended mode register do not have default values. if they are not programmed during the initialization sequence, it may lead to unspecified operation, all banks have to be in idle state prior to adjusting mrs and emrs set. temperature range self refresh current (idd6) unit full array 1/2 array 1/4 array typ. max typ. max typ. max 85 c 400 500 300 400 250 350 ua 70 c 250 200 165 45 c 150 250 120 220 100 200 15 c 140 110 95 ba1=0 - full array - 1/2 array - 1/4 array partial self refresh area ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=1 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0
- 15 - k4m51323pi-hg60 datasheet mobile sdr sdram rev. 1.0 k4m51323pi-hg75 17.0 burst sequence 17.1 burst length = 4 17.2 burst length = 8 initial address sequential interleave a1 a0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 initial address sequential interleave a2 a1 a0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

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